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Phone : +90 (216) 564 90 00

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E-mail: info@ozyegin.edu.tr

Dec 31, 2020 - Jan 05, 2021

Thesis Defense - İlkin Aliyev (MSEE)

 

Ilkin Aliyev - M.Sc.

Prof. H. Fatih Uğurdağ – Advisor

Assoc. Prof. Ali Akoğlu – Advisor

Date: 04.01.2021

Time: 17:00

Location: This meeting will be held ONLINE. Please send an e-mail to gizem.bakir@ozyegin.edu.tr in order to participate in this defense.

 

Converging towards FPGA Specific Design Decisions made on a List Scheduling Algorithm for Effective Execution

Thesis Committee:

Prof. H. Fatih Uğurdağ, Özyeğin University

Asst. Prof. Kadir Durak, Özyeğin University

Prof. Nizamettin Aydın, Yıldız Yechnical University

Abstract:

As heterogeneous computing becomes prevalent in emerging computing systems, mapping applications on to multiple processing elements (PEs) proves to be nontrivial. Heterogeneous Earliest Finish Time (HEFT) algorithm is an already existing scheduler that aims to minimize the total execution time of an application. The paradigm of HEFT is such that it accepts an acyclic task graph as input at run-time and assigns/schedules the precompiled atomic tasks to PEs.

HEFT stands out among many such schedulers not only in terms of producing shorter schedules but also in terms of its own short execution time. However, in real-time applications, the lower the latency, the better it is. To the best of our knowledge, this work is the only work that implements HEFT in hardware (on FPGA) further lowering its latency from milliseconds to as much as less than a microsecond. Porting HEFT to hardware has been challenging as data dependencies limit the amount of parallelism. Design of an efficient memory access pattern as well as an “incremental sorter” were key enablers in reducing the latency of the hardware implementation. We also integrated our FPGA-HEFT into an ARM-based SoC and validated its functionality using a realistic workload.

Bio: 

Ilkin Aliyev completed his bachelor’s degree in Electronics and Communications Engineering from Yildiz Technical University in 2018. After graduating, he started his master’s education under the supervision of Prof. H. Fatih Ugurdag in Electrical and Electronics Engineering at Ozyegin University in 2018. While studying master education, he became a member of “nEMESysLab” that is led by Prof. H. Fatih Ugurdag. Since 2019, he has been working on his master thesis project which addresses scheduling problems in multicore heterogeneous systems.